1. Field of the Invention
The present invention relates to a synchronization method and related apparatus, and more particularly to a method and related device for synchronizing data reception in a display device.
2. Description of the Prior Art
In a flat display, a driving system consists of a timing controller, source drivers and gate drivers. The timing controller receives low voltage differential signals (LVDS), and thereby generates data content attempted to be displayed on a panel of the flat display. The data content is transmitted to the source drivers via at least one transmission interface, and the source drivers convert the received data content into analog voltage driving signals for driving the panel. Various types of the transmission interfaces are used between the timing controller and the source drivers. A multilevel differential signaling interface, a reduced swing differential signaling (RSDS) interface and a mini-low voltage differential signaling (mini-LVDS) interface are usually utilized for transmission of data and clock signals. The multilevel differential signaling interface operates with differential signals featuring multiple current intensities, and thereby the current intensity and direction are jointly used for encoding a signal type and related logic state. The multilevel differential signaling interface is considered a combination of multiple RSDS interfaces with different signal levels and thus can carry more data. A transistor-to-transistor logic (TTL) signaling interface is utilized for transmission of control signals, such as a synchronization signal or a polarity signal. In addition, the signal transmission manners include cascading, bus type and dedicated type signaling manners.
In the source driver, a synchronization signal provided by the timing controller controls the time of outputting the voltage driving signals. Please refer to FIGS. 1-3, which illustrate schematic diagrams of driving systems 10, 20, and 30 adopting different transmission architecture according to display devices of the prior art. The driving systems 10-30 include a timing controller TCON and source drivers CD(N−2), CD(N−1), and CD(N). The timing controller TCON transmits a synchronization signal SYNC in transistor-to-transistor logic (TTL) signal form and transmits a clock and data signals in differential signal form.
In the driving system 10, a synchronization signal SYNC and a clock signal CLK are both transmitted to the source drivers CD(N−2)-CD(N) in the bus type manner. The data signals DATA1-DATA3, each of which is a differential signaling pair, are transmitted in the dedicated type manner providing independent transmission lines for each data signal.
In the driving system 20, the synchronization signal SYNC is transmitted to the source driver CD(N−2)-CD(N) via a bus. The clock signal CLK is transmitted from a timing controller TCON to the source driver CD(N) in the cascading manner. Each of the data signal DATA1-DATA3 has two differential signaling pairs and are transmitted in the dedicated type manner providing four transmission lines for each data signal.
In the driving system 30, the synchronization signal SYNC is transmitted in the cascading manner. Clock signals CLK1-CLK3 are respectively transmitted to the source drivers CD(N−2)-CD(N) in the dedicated type manner. Data signals DATA1-DATA3 are also transmitted in the dedicated type manner, and each data signal has a differential signal pair.
In the driving systems 10-30, the synchronization signal SYNC functions to notify every source driver of the time the timing controller TCON transmits the first data signal. After the synchronization signal SYNC is transmitted, the timing controller TCON waits a predetermined amount of a half cycle period and then transmits the first data signal. On the other hand, the source drivers CD(N−2)-CD(N) wait the same amount of the half cycle period when receiving the corresponding synchronization signal SYNC, and then begin to receive signals. The first bit of the received signals is recognized as the first data signal bit.
For seeking users' satisfaction, the trend of the display moves toward large panel size, and therefore the signaling lines coupling to the timing controller and different source drivers have greater and greater line length difference. In this situation, the signaling lines corresponding to different source drivers work under heavily different loads, effecting rising and falling rates of transmission signals. In addition, the synchronization signal in TTL signal form has larger amplitude than the signals in differential signal form. As a result, the synchronization signal requires longer time to change its logic state.
Please refer to FIGS. 4 and 5, which illustrate schematic diagrams of received signal waveforms of source drivers CD(N−2)-CD(N) according to the driving systems 10, 20, and 30 used in a large-panel display. FIG. 4 shows the synchronization signal SYNC affected by load effect, whereas FIG. 5 shows the synchronization signal SYNC affected by the signaling line length. Only waveforms S2 and S3 in FIGS. 4 and 5 are different, and other elements are the same. In FIGS. 4 and 5, the source drivers CD(N−2)-CD(N) are configured to begin to receive a data signal DATA two half clock cycle periods later after receiving the synchronization signal SYNC. A waveform S1 is an ideal waveform of the synchronization signal SYNC, rising over a high level threshold, 0.7× the maximum level of the synchronization signal SYNC, within a half clock cycle period C1. In an ideal, correct operation, the source drivers CD(N−2)-CD(N) shall recognize a signal duration A as the first data bit. However, due to different skew rates caused by variant loads to the synchronization signal, the waveforms S2 and S3, corresponding to the source drivers CD(N−1) and CD(N), are delayed and thereby rise to the high level within clock durations C2 and C3 respectively. Therefore, the source drivers CD(N−1) and CD(N) mistakenly recognize signal durations B and C as the first data bit respectively.
In addition, the time the synchronization signal SYNC arrives the source drivers CD(N−2)-CD(N) could be greatly different due to great length difference among the corresponding signaling lines. The waveforms S2 and S3 reveal that the synchronization signal SYNC arrives the source drivers CD(N−1) and CD(N) within the clock durations C2 and C3. In this situation, the source drivers CD(N−1) and CD(N) also mistakenly recognize signal durations B and C as the first data bit respectively.
In the prior art, the synchronization signal for notifying the source drivers of the time to prepare for data reception has the TTL signal form, and is transmitted in the bus type or cascading manner. In addition, the length differences among the signaling lines are large enough so that the time difference that the synchronization signal arrives different source drivers can be larger than a half cycle period, thereby resulting in erroneous data reception in the source drivers.